1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304

#!/usr/bin/env python
#-*- coding:utf-8 -*-
import sys
import operator
import re
import os
import os.path

#Ignore comments Begin
#--------------------------------------------------------
def ignore_comments(line_val, nextline_is_comment):
    line_nocomment=re.sub('//[\s\S]*', '', line_val)           #Ignore comments(//)
    line_nocomment=re.sub('/\*[\s\S]*\*/', '', line_nocomment) #Ignore comments(/* */)
    line_nocomment=line_nocomment.strip()                      #Ignore Spaces(head and tail of line_nocomment)

    #Ignore comments(/* */ Cross-line_nocomment)
    currentline_is_comment=nextline_is_comment
    if "/*" in line_nocomment:
        nextline_is_comment=True
        line_nocomment=re.sub('/\*[\s\S]*', '', line_nocomment) #Ignore comments
    if "*/" in line_nocomment:
        nextline_is_comment=False
        currentline_is_comment=False
        line_nocomment=re.sub('[\s\S]*\*/', '', line_nocomment) #Ignore comments
    if currentline_is_comment:
        line_nocomment=re.sub('[\s\S]*', '', line_nocomment)    #Ignore comments

    line_nocomment=line_nocomment.strip() #Ignore Spaces(head and tail of line_nocomment)
    if line_nocomment == '':
        line_nocomment="/*LINE_IS_COMMENT*/"

    return line_nocomment, nextline_is_comment
#--------------------------------------------------------
#Ignore comments End

#Fetch Keywords Add To Dict Begin
#--------------------------------------------------------
def fetch_keywords(line_val):
    line_val=re.sub('input ', '', line_val)
    line_val=re.sub('output ', '', line_val)
    line_val=re.sub('wire ', '', line_val)
    line_val=re.sub('reg ', '', line_val)
    line_val=re.sub('assign ', '', line_val)
    line_val=re.sub('[<]?=[\S\s]*', '', line_val)
    line_val=line_val.strip()

    signal_width=re.findall('\[[` a-zA-Z0-9_:\-]+\]', line_val)
    if len(signal_width) != 0 :
        signal_name=re.sub('\[[` a-zA-Z0-9_:\-]+\]', '', line_val)
        signal_name=signal_name.strip()
        signal_width_max=''.join(re.findall('\[[\s]*([`a-zA-Z0-9_\-]+)', line_val))
        signal_width_min=''.join(re.findall('([`a-zA-Z0-9_\-]+)[\s]*\]', line_val))
    else:
        signal_name=line_val.strip()
        signal_width_max='0'
        signal_width_min='0'

    return signal_name, signal_width_max, signal_width_min
#--------------------------------------------------------
#Fetch Keywords Add To Dict End

#Add Keys To Dict Begin
#--------------------------------------------------------
def add_keys_to_dict(type_val,
                     input_dict,
                     output_dict,
                     wire_dict,
                     reg_dict,
                     addwire_dict0,
                     addreg_dict0,
                     addwire_dict1,
                     addreg_dict1,
                     key_val,
                     key_width_max,
                     key_width_min):

    if type_val == 'output_type':
        output_dict.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})
        return
    if type_val == 'input_type':
        input_dict.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})
        return
    if type_val == 'wire_type':
        wire_dict.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})
        return
    if type_val == 'reg_type':
        reg_dict.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})
        return

    input_check=input_dict.has_key(key_val)
    output_check=output_dict.has_key(key_val)
    reg_check=reg_dict.has_key(key_val)
    wire_check=wire_dict.has_key(key_val)
    addwire0_check=addwire_dict0.has_key(key_val)
    addreg0_check=addreg_dict0.has_key(key_val)
    addwire1_check=addwire_dict1.has_key(key_val)
    addreg1_check=addreg_dict1.has_key(key_val)
    if key_width_max.isdigit() and key_width_min.isdigit():
        if type_val == 'addwire_type':
            if addwire0_check:
                signal_width_max=addwire_dict0[key_val]['width_max']
                signal_width_min=addwire_dict0[key_val]['width_min']
                if int(key_width_max) > int(signal_width_max):
                    addwire_dict0[key_val]['width_max']=key_width_max
                if int(key_width_min) < int(signal_width_min):
                    addwire_dict0[key_val]['width_min']=key_width_min
            elif output_check or addwire1_check or wire_check:
                pass
            else:
                addwire_dict0.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})

        if type_val == 'addreg_type':
            if addreg0_check:
                signal_width_max=addreg_dict0[key_val]['width_max']
                signal_width_min=addreg_dict0[key_val]['width_min']
                if int(key_width_max) > int(signal_width_max):
                    addreg_dict0[key_val]['width_max']=key_width_max
                if int(key_width_min) < int(signal_width_min):
                    addreg_dict0[key_val]['width_min']=key_width_min
            elif addreg1_check or reg_check:
                pass
            else:
                addreg_dict0.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})

    else:
        update_width_max=''.join(re.findall('`[a-zA-Z0-9]+[\s]*\-[\s]*1', key_width_max))
        update_width_min=''.join(re.findall('0', key_width_min))
        if type_val == 'addwire_type':
            if addwire0_check:
                addwire_dict0.pop('key_val')
            if addwire1_check:
                if update_width_max != '':
                    addwire_dict1[key_val]['width_max']=key_width_max
                if update_width_min != '':
                    addwire_dict1[key_val]['width_min']=key_width_min
                pass
            elif output_check or wire_check:
                pass
            else:
                addwire_dict1.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})

        if type_val == 'addreg_type':
            if addreg0_check:
                addreg_dict0.pop('key_val')
            if addreg1_check:
                if update_width_max != '':
                    addwire_dict1[key_val]['width_max']=key_width_max
                if update_width_min != '':
                    addwire_dict1[key_val]['width_min']=key_width_min
                pass
            elif reg_check:
                pass
            else:
                addreg_dict1.update({key_val:{'width_max':key_width_max, 'width_min':key_width_min}})

    return
#--------------------------------------------------------
#Add Keys To Dict End

#Print Declare Begin
#--------------------------------------------------------
def print_declare(addwire_dict0, addreg_dict0, addwire_dict1, addreg_dict1):
    addwire_dict0_keys=addwire_dict0.keys()
    addwire_dict1_keys=addwire_dict1.keys()
    addreg_dict0_keys=addreg_dict0.keys()
    addreg_dict1_keys=addreg_dict1.keys()

    print "    // Begin auto declaration"

    print "    // Please double check the declaration with macro"
    for key in addwire_dict1_keys:
        if addwire_dict1[key]['width_max'] == addwire_dict1[key]['width_min']:
            declaration="    wire " + "[" + addwire_dict1[key]['width_max'] + "]" + " " + key + ";"
        else:
            declaration="    wire " + "[" + addwire_dict1[key]['width_max'] + ":" + addwire_dict1[key]['width_min'] + "]" + " " + key + ";"
        print declaration
    for key in addreg_dict1_keys:
        if addreg_dict1[key]['width_max'] == addreg_dict1[key]['width_min']:
            declaration="    reg  " + "[" + addreg_dict1[key]['width_max'] + "]" + " " + key + ";"
        else:
            declaration="    reg  " + "[" + addreg_dict1[key]['width_max'] + ":" + addreg_dict1[key]['width_min'] + "]" + " " + key + ";"
        print declaration
    print "    // Please double check the declaration with macro"

    for key in addwire_dict0_keys:
        if addwire_dict0[key]['width_max'] == '0':
            declaration="    wire " + "            " + key + ";"
        else:
            declaration="    wire " + "[" + addwire_dict0[key]['width_max'].rjust(4) + ":" + addwire_dict0[key]['width_min'].rjust(4) + "]" + " " + key + ";"
        print declaration
    for key in addreg_dict0_keys:
        if addreg_dict0[key]['width_max'] == '0':
            declaration="    reg  " + "            " + key + ";"
        else:
            declaration="    reg  " + "[" + addreg_dict0[key]['width_max'].rjust(4) + ":" + addreg_dict0[key]['width_min'].rjust(4) + "]" + " " + key + ";"
        print declaration

    print "    // End auto declaration"
#--------------------------------------------------------
#Print Declare End

#Main Program Begin
#--------------------------------------------------------

#open verilog file
#=================
try:
    vfile=open(sys.argv[1], 'r')
    alllines=vfile.readlines()
except (IOError,OSError) as reason:
    print('文件出错了！错误原因是：\n' + str(reason))
finally:
    vfile.close()
#=================

#line process
#=================
input_dict={}
output_dict={}
wire_dict={}
reg_dict={}
addwire_dict0={}
addreg_dict0={}
addwire_dict1={}
addreg_dict1={}

nextline_is_comment=False
currentline_is_comment=False
line_num=0
for line in alllines:
    line_num+=1

    line_nocomment, nextline_is_comment=ignore_comments(line, nextline_is_comment)
    if line_nocomment == "/*LINE_IS_COMMENT*/":
        continue
    #print "Line Nocomment:", line_nocomment

    output_regex=re.compile('(output[\s]*(?:\[[` a-zA-Z0-9_:\-]+\])?[\s]*[a-zA-Z0-9_]+[\s]*)')
    input_regex=re.compile('(input[\s]*(?:\[[` a-zA-Z0-9_:\-]+\])?[\s]*[a-zA-Z0-9_]+[\s]*)')
    wire_regex=re.compile('(wire[\s]*(?:\[[` a-zA-Z0-9_:\-]+\])?[\s]*[a-zA-Z0-9_]+[\s]*)')
    reg_regex=re.compile('(reg[\s]*(?:\[[` a-zA-Z0-9_:\-]+\])?[\s]*[a-zA-Z0-9_]+[\s]*)')
    addwire_regex=re.compile('(assign[\s]*[a-zA-Z0-9_]+[\s]*(?:\[[` a-zA-Z0-9_:\-]+\])?[\s]*[<]?=[^=><!~]+)')
    addreg_regex=re.compile('([\s]*[a-zA-Z0-9_]+[\s]*(?:\[[` a-zA-Z0-9_:\-]+\])?[\s]*[<]?=[^=><!~]+)')
    output_line=output_regex.findall(line_nocomment)
    input_line=input_regex.findall(line_nocomment)
    wire_line=wire_regex.findall(line_nocomment)
    reg_line=reg_regex.findall(line_nocomment)
    addreg_line=addreg_regex.findall(line_nocomment)
    addwire_line=addwire_regex.findall(line_nocomment)

    if len(output_line) != 0:
        type_val="output_type"
        signal_name, signal_width_max, signal_width_min = fetch_keywords(''.join(output_line))
    elif len(input_line) != 0:
        type_val="input_type"
        signal_name, signal_width_max, signal_width_min = fetch_keywords(''.join(input_line))
    elif len(wire_line) != 0:
        type_val="wire_type"
        signal_name, signal_width_max, signal_width_min = fetch_keywords(''.join(wire_line))
    elif len(reg_line) != 0:
        type_val="reg_type"
        signal_name, signal_width_max, signal_width_min = fetch_keywords(''.join(reg_line))
    elif len(addwire_line) != 0: #Note: wire should be judged before reg
        type_val="addwire_type"
        signal_name, signal_width_max, signal_width_min = fetch_keywords(''.join(addwire_line))
    elif len(addreg_line) != 0:
        type_val="addreg_type"
        signal_name, signal_width_max, signal_width_min = fetch_keywords(''.join(addreg_line))
    else:
        continue
#    print "##Type Vale       :", type_val
#    print "##Signal_Name     :", signal_name
#    print "##Signal_Width_Max:", signal_width_max
#    print "##Signal_Width_Min:", signal_width_min
#    print "\n"

    add_keys_to_dict(type_val,
                     input_dict,
                     output_dict,
                     wire_dict,
                     reg_dict,
                     addwire_dict0,
                     addreg_dict0,
                     addwire_dict1,
                     addreg_dict1,
                     signal_name,
                     signal_width_max,
                     signal_width_min)
#=================

#print declare
#=================
#print addwire_dict0
#print ""
#print addwire_dict1
#print ""
#print addreg_dict0
#print ""
#print addreg_dict1

print_declare(addwire_dict0, addreg_dict0, addwire_dict1, addreg_dict1)
#=================
#--------------------------------------------------------
#Main Program End

1

assign {sig_a, sig_b} = 2'b11;

1
2

python verilog_auto_declare.py  verilog_filename.v
python verilog_auto_declare.py  verilog_filename.v >autodeclare.log

1
2
3
4
5
6

#!/bin/bash

python ~/Treasury/tools_and_drives/verilog_auto_declare/verilog_auto_declare.py $1 >autodeclare.log
sed '/\/*AUTO DECLARE/r autodeclare.log' $1 > print_declare.v
mv print_declare.v $1
rm -rf autodeclare.log

1
2
3
4

#!/bin/bash

sed '/\/\/ Begin auto declaration/,/End auto declaration/c \' $1 >delete_declare.v
mv delete_declare.v $1

1
2

chmod 755 print_declare.sh
chmod 755 print_declare.sh

1
2
3

#verilog_auto_declare
alias print_declare='~/Treasury/tools_and_drives/verilog_auto_declare/print_declare.sh'
alias delete_declare='~/Treasury/tools_and_drives/verilog_auto_declare/delete_declare.sh'

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109

//-------------------------------------------------------------------------
// Title         :
// Project       :
//-------------------------------------------------------------------------
// File name     :
// Author        :
// Created       :
// Last modified :
//-------------------------------------------------------------------------
// Description   :
//
// This block does the following operations:
//   -
//   -
//-------------------------------------------------------------------------
//   This file is a confidential and proprietary property of XXX and the
// possession or use of this requires a written license from XXX.
//
//   Copyright (c) 2020 XXX Technology Co., Ltd. ALL rights reserved.
//-------------------------------------------------------------------------

module auto_declare_test(/*AUTOARG*/
// Outputs
dout_a, dout_b,
// Inputs
clk, din_a, din_b, din_c, dout_c
);
input                clk;
input                din_a;
input [3:0]          din_b;
input [`C_WIDTH-1:0] din_c;
output               dout_a;
output [5:0]         dout_b;
input [`C_WIDTH-1:0] dout_c;

wire                w_aaaa;
wire [3:0]          w_bbbb;
wire [`WC_WITH-1:0] w_cccc;
reg                 r_aaaa;
reg  [3:0]          r_bbbb;
reg  [`RC_WITH-1:0] r_cccc;

/*AUTO DECLARE*/

//wire                w_aa;
//wire [3:0]          w_bb;
//wire [`WC_WITH-1:0] w_cc;
//reg                 r_aa;
//reg  [3:0]          r_bb;
//reg  [`RC_WITH-1:0] r_cc;
//assign w_aa  = 1'b1;
//assign w_xx  = 1'b1;
//assign w_yy  = w_aa ? 1'b1 :
//                      1'b0 ;
//always(*) r_bb[3:0] = 4'b1100;
//always(*)
//    r_aa = 1'b1;
//always@(posedge clk)begin
//    r_xx <= w_aa;
//    r_yy <= w_bb[0];
//    r_zz <= w_cc[3];
//end

/*
wire                w_aaa;
wire [3:0]          w_bbb;
wire [`WC_WITH-1:0] w_ccc;
reg                 r_aaa;
reg  [3:0]          r_bbb;
reg  [`RC_WITH-1:0] r_ccc;
assign w_aaa  = 1'b1;
assign w_xxx  = 1'b1;
assign w_yyy  = w_aaa ? 1'b1 :
                       1'b0 ;
always(*) r_bbb[3:0] = 4'b1100;
always(*)
    r_aaa = 1'b1;
always@(posedge clk)begin
    r_xxx <= w_aaa;
    r_yyy <= w_bbb[0];
    r_zzz <= w_ccc[3];
end
*/

assign w_aaaa  = 1'b1;
assign w_bbbb  = 1'b1;
assign w_cccc  = 1'b1;
assign w_xxxx  = 1'b1;
assign w_yyyy  = w_aaaa ? 1'b1 :
                          1'b0 ;
always(*) r_bbbb[3:0] = 4'b1100;/*coment
comment comment*/
always(*)//assign wccx[3:0] = 4'b1011;
    r_aaaa = 1'b1;/*assign wccxxxx[3:0] = 4'b1011;*/
always@(posedge clk)begin//wire yywcc;
    r_xxxx <= w_aaaa;/*wire [3:0] yywccy;
*/  r_yyyy <= w_bbbb[0];
    r_zzzz <= w_cccc[3];/*assign dyyyy[3:0] = 4'b1011;
  */marco_aaaa [`AAAAWIDTH-1:0] = 8'h45;
    marco_bbbb [`BBBBWIDTH-1:0] = 8'h45;
end

assign marco_xxxx [`XXXXWIDTH-1:0] = 8'h45;
assign marco_yyyy [`YYYYWIDTH] = 1'b1;

assign wccx [2] = 1'b1;
assign wccy [1] = 1'b1;

endmodule // auto_declare_test

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124

//-------------------------------------------------------------------------
// Title         :
// Project       :
//-------------------------------------------------------------------------
// File name     :
// Author        :
// Created       :
// Last modified :
//-------------------------------------------------------------------------
// Description   :
//
// This block does the following operations:
//   -
//   -
//-------------------------------------------------------------------------
//   This file is a confidential and proprietary property of XXX and the
// possession or use of this requires a written license from XXX.
//
//   Copyright (c) 2020 XXX Technology Co., Ltd. ALL rights reserved.
//-------------------------------------------------------------------------

module auto_declare_test(/*AUTOARG*/
// Outputs
dout_a, dout_b,
// Inputs
clk, din_a, din_b, din_c, dout_c
);
input                clk;
input                din_a;
input [3:0]          din_b;
input [`C_WIDTH-1:0] din_c;
output               dout_a;
output [5:0]         dout_b;
input [`C_WIDTH-1:0] dout_c;

wire                w_aaaa;
wire [3:0]          w_bbbb;
wire [`WC_WITH-1:0] w_cccc;
reg                 r_aaaa;
reg  [3:0]          r_bbbb;
reg  [`RC_WITH-1:0] r_cccc;

/*AUTO DECLARE*/
    // Begin auto declaration
    // Please double check the declaration with macro
    wire [`YYYYWIDTH] marco_yyyy;
    wire [`XXXXWIDTH-1:0] marco_xxxx;
    reg  [`AAAAWIDTH-1:0] marco_aaaa;
    reg  [`BBBBWIDTH-1:0] marco_bbbb;
    // Please double check the declaration with macro
    wire             w_yyyy;
    wire             w_xxxx;
    wire [   1:   1] wccy;
    wire [   2:   2] wccx;
    reg              r_yyyy;
    reg              r_zzzz;
    reg              r_xxxx;
    // End auto declaration

//wire                w_aa;
//wire [3:0]          w_bb;
//wire [`WC_WITH-1:0] w_cc;
//reg                 r_aa;
//reg  [3:0]          r_bb;
//reg  [`RC_WITH-1:0] r_cc;
//assign w_aa  = 1'b1;
//assign w_xx  = 1'b1;
//assign w_yy  = w_aa ? 1'b1 :
//                      1'b0 ;
//always(*) r_bb[3:0] = 4'b1100;
//always(*)
//    r_aa = 1'b1;
//always@(posedge clk)begin
//    r_xx <= w_aa;
//    r_yy <= w_bb[0];
//    r_zz <= w_cc[3];
//end

/*
wire                w_aaa;
wire [3:0]          w_bbb;
wire [`WC_WITH-1:0] w_ccc;
reg                 r_aaa;
reg  [3:0]          r_bbb;
reg  [`RC_WITH-1:0] r_ccc;
assign w_aaa  = 1'b1;
assign w_xxx  = 1'b1;
assign w_yyy  = w_aaa ? 1'b1 :
                       1'b0 ;
always(*) r_bbb[3:0] = 4'b1100;
always(*)
    r_aaa = 1'b1;
always@(posedge clk)begin
    r_xxx <= w_aaa;
    r_yyy <= w_bbb[0];
    r_zzz <= w_ccc[3];
end
*/

assign w_aaaa  = 1'b1;
assign w_bbbb  = 1'b1;
assign w_cccc  = 1'b1;
assign w_xxxx  = 1'b1;
assign w_yyyy  = w_aaaa ? 1'b1 :
                          1'b0 ;
always(*) r_bbbb[3:0] = 4'b1100;/*coment
comment comment*/
always(*)//assign wccx[3:0] = 4'b1011;
    r_aaaa = 1'b1;/*assign wccxxxx[3:0] = 4'b1011;*/
always@(posedge clk)begin//wire yywcc;
    r_xxxx <= w_aaaa;/*wire [3:0] yywccy;
*/  r_yyyy <= w_bbbb[0];
    r_zzzz <= w_cccc[3];/*assign dyyyy[3:0] = 4'b1011;
  */marco_aaaa [`AAAAWIDTH-1:0] = 8'h45;
    marco_bbbb [`BBBBWIDTH-1:0] = 8'h45;
end

assign marco_xxxx [`XXXXWIDTH-1:0] = 8'h45;
assign marco_yyyy [`YYYYWIDTH] = 1'b1;

assign wccx [2] = 1'b1;
assign wccy [1] = 1'b1;

endmodule // auto_declare_test